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Author Topic: VHDL vector  (Read 612 times)
agu_rn
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« on: May 30, 2017, 02:08:51 AM »


how can i see the inputs or outputs if they are vectors?

Because I define the output like a vector :
OutputA: out std_logic_vector(3 downto 0);

In the vhdl code.

But in Tina I only see one output : outputA

Thanks

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etl17
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« Reply #1 on: June 01, 2017, 10:19:54 AM »

I wonder if this is related to the fact that viewing busses in diagrams also only brings the first output as well.
Is this tracked as an open issue?
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CDRIVE
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« Reply #2 on: June 02, 2017, 04:10:44 PM »

I can't speak to your VHDL code because I've never written any. The Bus issue is another issue though. As you may have discovered in other topics it's a known bug.

Chris
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___________________________________________
Working with electricity can be dangerous. Any information that I post, including schematics and or code are intended for educational purposes only. No warranty of circuit or code suitability is expressed or implied. Proceed at your own risk.
Endre
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« Reply #3 on: June 11, 2017, 01:06:14 PM »

Hi,

I have contacted the support with it a few days ago. They replied that a Voltage Pin have to be connected into the one wire vector, and the Voltage Pin have to be configured as Digital Output.
I haven't checked yet that it is really working (I have tried, but other things seems to be dead in my schematic).
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Endre
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« Reply #4 on: June 11, 2017, 02:22:28 PM »

Attaching Voltage Pin, configured as Digital Output, into the VHDL vector wire is working. You'll see the vector values in the signal browser after a transient analysis.
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CDRIVE
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« Reply #5 on: June 19, 2017, 09:12:14 PM »

Since you didn't post the schematic or the .TSC no one here can help in finding why parts of your circuit aren't working.

Chris
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___________________________________________
Working with electricity can be dangerous. Any information that I post, including schematics and or code are intended for educational purposes only. No warranty of circuit or code suitability is expressed or implied. Proceed at your own risk.
agu_rn
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« Reply #6 on: July 09, 2017, 01:41:44 PM »

Hi, everybody! I found a solution. The mistake was that I chose DC interactive mode, instead of VHDL:



 The wire works like a bus but if I want to work with cables I have to write a new VHDL code (macro).

Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity NTSS7 is
          Port ( I2 : in STD_LOGIC_VECTOR (6 downto 0);
                 Q20 : out STD_LOGIC;
                 Q21 : out STD_LOGIC;
                 Q22 : out STD_LOGIC;
                 Q23 : out STD_LOGIC;
                 Q24 : out STD_LOGIC;
                 Q25 : out STD_LOGIC;
                 Q26 : out STD_LOGIC);
end NTSS7;
architecture Behavioral of NTSS7 is
       begin
             PROCESS (I2)
                 BEGIN
                    Q20 <= I2(0);
                    Q21 <= I2(1);
                    Q22 <= I2(2);
                    Q23 <= I2(3);
                    Q24 <= I2(4);
                    Q25 <= I2(5);
                    Q26 <= I2(6);                   
                       
                 END PROCESS;
end Behavioral;

Here I add a screenshot:

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