Hi, everybody! I found a solution. The mistake was that I chose DC interactive mode, instead of VHDL:

The wire works like a bus but if I want to work with cables I have to write a new VHDL code (macro).

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity NTSS7 is

Port ( I2 : in STD_LOGIC_VECTOR (6 downto 0);

Q20 : out STD_LOGIC;

Q21 : out STD_LOGIC;

Q22 : out STD_LOGIC;

Q23 : out STD_LOGIC;

Q24 : out STD_LOGIC;

Q25 : out STD_LOGIC;

Q26 : out STD_LOGIC);

end NTSS7;

architecture Behavioral of NTSS7 is

begin

PROCESS (I2)

BEGIN

Q20 <= I2(0);

Q21 <= I2(1);

Q22 <= I2(2);

Q23 <= I2(3);

Q24 <= I2(4);

Q25 <= I2(5);

Q26 <= I2(6);

END PROCESS;

end Behavioral;

Here I add a screenshot: