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Author Topic: VHDL vector  (Read 544 times)
Posts: 3

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« on: May 30, 2017, 01:57:07 AM »

how can i see the inputs or outputs if they are vectors?

Because I define the output like a vector :
OutputA: out std_logic_vector(3 downto 0);

In the vhdl code.

But in Tina I only see one output : outputA

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