DesignSoft
October 17, 2017, 12:53:18 PM *
Welcome, Guest. Please login or register.
Did you miss your activation email?

Login with username, password and session length
News: Welcome to TINACloud, the cloud based version of TINA, running in your browser without any installation and anywhere in the world. For limited time, now you can get it for free if you purchase a new license or upgrade to v10 version of TINA at www.tinacloud.com.  With this great extension you can present or modify your designs wherever you are in the world and even while travelling.

We are eager to hear from you any comments and feedback.
 
 
   Home   Help Search Login Register  
Pages: [1]
  Print  
Author Topic: VHDL vector  (Read 403 times)
agu_rn
Newbie
*
Posts: 3


View Profile
« on: May 30, 2017, 01:57:07 AM »

how can i see the inputs or outputs if they are vectors?

Because I define the output like a vector :
OutputA: out std_logic_vector(3 downto 0);

In the vhdl code.

But in Tina I only see one output : outputA

Thanks
Logged
Pages: [1]
  Print  
 
Jump to:  

Powered by MySQL Powered by PHP Powered by SMF 1.1.9 | SMF © 2006-2009, Simple Machines LLC Valid XHTML 1.0! Valid CSS!