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 1 
 on: June 19, 2017, 09:12:14 PM 
Started by agu_rn - Last post by CDRIVE
Since you didn't post the schematic or the .TSC no one here can help in finding why parts of your circuit aren't working.

Chris

 2 
 on: June 12, 2017, 10:08:59 PM 
Started by Endre - Last post by Endre
I like to name VHDL files with .vhdl extension, Tina filters only for .VHD extension.
Remembering the good old CP/M times is nice, but now days even Windows can handle file extensions longer than 3 characters.

 3 
 on: June 12, 2017, 09:59:55 PM 
Started by Endre - Last post by Endre
Answer from support: Reference input have to be connected into GND.

This way it works.

 4 
 on: June 11, 2017, 02:31:01 PM 
Started by Endre - Last post by Endre
It's output is always 0, while the input varies from 0V into reference voltage. See picture.

 5 
 on: June 11, 2017, 02:22:28 PM 
Started by agu_rn - Last post by Endre
Attaching Voltage Pin, configured as Digital Output, into the VHDL vector wire is working. You'll see the vector values in the signal browser after a transient analysis.

 6 
 on: June 11, 2017, 01:06:14 PM 
Started by agu_rn - Last post by Endre
Hi,

I have contacted the support with it a few days ago. They replied that a Voltage Pin have to be connected into the one wire vector, and the Voltage Pin have to be configured as Digital Output.
I haven't checked yet that it is really working (I have tried, but other things seems to be dead in my schematic).

 7 
 on: June 02, 2017, 04:10:44 PM 
Started by agu_rn - Last post by CDRIVE
I can't speak to your VHDL code because I've never written any. The Bus issue is another issue though. As you may have discovered in other topics it's a known bug.

Chris

 8 
 on: June 01, 2017, 10:19:54 AM 
Started by agu_rn - Last post by etl17
I wonder if this is related to the fact that viewing busses in diagrams also only brings the first output as well.
Is this tracked as an open issue?

 9 
 on: May 30, 2017, 02:08:51 AM 
Started by agu_rn - Last post by agu_rn

how can i see the inputs or outputs if they are vectors?

Because I define the output like a vector :
OutputA: out std_logic_vector(3 downto 0);

In the vhdl code.

But in Tina I only see one output : outputA

Thanks


 10 
 on: May 30, 2017, 01:57:07 AM 
Started by agu_rn - Last post by agu_rn
how can i see the inputs or outputs if they are vectors?

Because I define the output like a vector :
OutputA: out std_logic_vector(3 downto 0);

In the vhdl code.

But in Tina I only see one output : outputA

Thanks

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